1. Field of the Invention
The present invention relates to improvements in the configuration of an active matrix display and, more particularly, to improvements in the configuration of a peripheral drive circuit for driving active matrix regions.
2. Description of the Related Art
An active matrix liquid crystal display comprising a substrate on which a peripheral drive circuit is integrated with other circuits is known. This common substrate is made of glass or quartz. Some TFTs are arranged in the active matrix circuit, while other TFTs are arranged in the peripheral drive circuit. This configuration is obtained by fabricating these two kinds of TFTs by the same process steps. A TFT is generally made of a thin film that has crystallinity and is represented as P-Si.
Peripheral drive circuits are classified into scanning drive circuit (gate drive circuit) and signal drive circuit (source drive circuit) in terms of function. Drive signals from the scanning drive circuit are supplied to the gate electrodes of TFTs or pixel transistors arranged in rows and columns within the active matrix circuit. Drive signals from the signal drive circuit (source drive circuit) are fed to the source electrodes of the TFTs or pixel transistors arranged in rows and columns.
Generally, the scanning drive circuit is required to be operated at tens of kilohertz to hundreds of kilohertz, while the signal drive circuit needs to be operated at several megahertz to tens of megahertz. However, TFTs obtained at present are guaranteed to operate only up to several megahertz. Therefore, fabricating the scanning drive circuit from TFTs presents no problems but where the signal drive circuit is constructed from TFTs, the required operation cannot be performed.
To avoid this problem, a polyphase driving method (data division method) has been used. In particular, an image data signal is divided into plural image data groups. Some of these data groups are simultaneously selected according to signals from a shift register circuit. Thus, the frequency at which the shift register circuit must operate can be scaled down. If the image data signal is divided by four, the operating frequency of the shift register circuit can be scaled down by a factor of 4. This polyphase driving method is described in Flat Panel Display, p. 182, Nikkei BP Corporation, Japan, 1994.
One example of the scanning drive circuit that divides a data signal into 8 groups is shown in FIG. 3, where a signal supplied from a shift register circuit 10 via a buffer circuit 11 causes a sampling circuit 13 to select some of image data signals supplied to the bus signal lines 12. The selected signals are sent to an active matrix circuit 15 via image signal lines 14. The bus signal lines 12 are 8 separate lines. In this configuration, 8 analog switch circuits are operated simultaneously in response to the output signal from one shift register circuit. Image signals are selected simultaneously from their respective bus signal lines corresponding to the 8 image signal lines (source lines).
A conductor pattern forming the bus signal lines shown in FIG. 3 is depicted in FIG. 4. Conducting lines D1xe2x80x2-D8xe2x80x2 are in contact with the bus signal lines and run to analog switches of the sampling circuit 102. Conducting lines a1-a8 run from the buffer circuit 101 to the analog switches of the sampling circuit 102.
It is observed that the image presented on the active matrix liquid crystal display of the structure shown in FIGS. 3 and 4 has a periodic stripe pattern. Careful observation of this stripe pattern reveals that it corresponds to the repetition of the conducting lines D1xe2x80x2-D8xe2x80x2 shown in FIG. 4. For example, the corresponding portions of the conducting lines D1xe2x80x2 and D8xe2x80x2 differ greatly in resistance and parasitic capacitance. The resistance difference is caused by the difference in the number of overlapping portions at the intersections of the conducting lines D1xe2x80x2-D8 and the conducting lines D1xe2x80x2-D8xe2x80x2.
More specifically, the conducting lines D1-D8 intersect with the conducting lines D1xe2x80x2-D8xe2x80x2, at locations, where the conducting lines of one group pass over the conducting lines of the other. Consequently, the metallization layer forming the conducting lines is thinned at these locations. Of course, this increases the resistance. Furthermore, at these intersections, capacitances are created between the intersecting conducting lines. Accordingly, the difference in the number of overlapping portions produces different total conductor resistances and different total parasitic capacitances, as shown in FIG. 5. It is to be noted that in FIG. 5, conducting lines from the buffer circuit are not taken into account.
In this situation, the signal traveling over the signal line D1 differs in mode of propagation from the signal traveling over the signal line D8. That is, the signal traveling over the signal line D8 has a larger signal component dissipating via parasitic capacitance than that of the signal traveling over the signal line D1. Therefore, the signal traveling over the signal line D8 is smaller in magnitude than the signal traveling over the signal line D1 provided that the same signal is supplied to both conducting lines. This tendency becomes more conspicuous with going from D1 toward D8, because more signal is lost due to conductor resistance and parasitic capacitance with going from D1 to D2, from D2 to D3, and so forth. As a result, different amounts of information are written to different pixels at the same time. In other words, different amounts of electric charge are stored on different pixels, giving rise to the aforementioned stripe pattern.
It is an object of the present invention to provide a technique for removing the stripe pattern produced by the above-described factors.
One display device in accordance with the present invention comprises a substrate on which an active matrix circuit, a peripheral drive circuit, and A (A is a natural number equal to or greater than 2) conducting lines are arranged. These conducting lines (hereinafter referred to as the image data signal lines) supply image data signals. Image signal lines and scanning signal lines are arranged in the active matrix circuit. The peripheral drive circuit has multiple stages of shift register circuits and a sampling circuit for selecting some of the image data signals according to signals from the shift register circuits. In the sampling circuit, image data signals to be supplied from the A image data lines to the A image signal lines are simultaneously selected in response to the output signal from one stage of shift register circuit. Of the A image data signal lines, (Axe2x88x921) lines meet dummy conducting lines.
In the above-described structure, one example of the above-described dummy conducting lines is a conductor pattern extending to a buffer circuit 201 from the conducting lines D2xe2x80x2-D8xe2x80x2, which in turn run to a sampling circuit 202 as shown in FIG. 1. Another example of the dummy lines consists of conducting lines that are connected with a common conducting line C placed at an appropriate potential but are disconnected from the conducting lines D2xe2x80x2-D8xe2x80x2, as shown in FIG. 7. In either case, A=8, and the (Axe2x88x921) conducting lines D1-D7 intersect with the dummy lines.
A specific example of the configuration of another display device in accordance with the invention is shown in FIG. 2. In this example, A=8. This display device comprises a substrate on which an active matrix circuit 25, a peripheral drive circuit, and A (A is a natural number equal to or greater than 2; in this case A=8) conducting lines or bus lines 22 are arranged. These conducting lines (hereinafter referred to also as the image data signal lines) supply image data signals. Image signal lines 24 and scanning signal lines are arranged in the active matrix circuit 25. The peripheral drive circuit has multiple stages of shift register circuits 20 and a sampling circuit 23 for selecting some image data signals according to signals from the shift register circuits 20. In the sampling circuit 23, image data signals to be supplied from the A image data signal lines 22 to the A image signal lines are simultaneously selected in response to the output signal from one stage of shift register circuit. All of those conducting lines that are in contact with the A image data signal lines 22 and extend to the sampling circuit 23 overlap the A image data signal lines 22 at A locations.
In this structure, all the bus lines 22 intersect at the same number of locations as the conducting lines running to the sampling circuit 23. Therefore, the resistance and capacitance created at each intersection can be made uniform for every bus line. Consequently, it is possible to compensate for variations in loss of signal traveling over the bus lines 22.
A further display device in accordance with the present invention comprises a substrate on which an active matrix circuit, a peripheral drive circuit, and A (A is a natural number equal to or greater than 2) conducting lines are arranged. These conducting lines (hereinafter referred to as the image data signal lines) supply image data signals. Image signal lines and scanning signal lines are a-ranged in the active matrix circuit. The peripheral drive circuit has multiple stages of shift register circuits and a sampling circuit for selecting some of the image data signals according to signals from the shift register circuits. In the sampling circuit, image data signals to be supplied from the A image data signal lines to the A image signal lines are simultaneously selected in response to the output signal from one stage of shift register circuit. All of those conducting lines that are in contact with the A image data signal lines and extend to the sampling circuit overlap at the same number of locations as the A image data signal lines.
A still other display device in accordance with the present invention comprises a substrate on which an active matrix circuit, a peripheral drive circuit, and A (A is a natural number equal to or greater than 2) conducting lines are arranged. These conducting lines (hereinafter referred to as the image data signal lines) supply image data signals. Image signal lines and scanning signal lines are arranged in the active matrix circuit. The peripheral drive circuit has multiple stages of shift register circuits and a sampling circuit for selecting some of the image data signals according to signals from the shift register circuits. In the sampling circuit, image data signals to be supplied from the A image data signal lines to the A image signal lines are simultaneously selected in response to the output signal from one stage of shift register circuit. A sampling circuit input lines extend to the sampling circuit and are in contact with the A image data signal lines. Of these A sampling circuit input lines, (Axe2x88x921) lines have a dummy pattern extending away from the sampling circuit.
The conducting lines D1xe2x80x2-D8xe2x80x2 shown in FIG. 1 provide an example of the above-described dummy pattern. The provision of this dummy pattern averages out conductor resistances and parasitic capacitances of the conducting lines D1-D8 that supply A (in the case of FIG. 1, A=8) image data items.
Other objects and features of the invention will appear in the course of the description thereof, which follows.